In order to meet demands for higher integration of an LSI (a large scale integrated circuit), and faster signal propagation, a design rule for the LSI has lately been on a reduction trail, and reduction has been implemented in respect of an interconnection pitch, a line width, an interval between interconnections, and the number of interlayer connection holes (vias) for connecting the interconnections with each other. Further, in order to cope with higher integration of a semiconductor device, formation of interconnections in a multilayer structure have been under study, and there has been a further increase in a ratio of a depth of an interconnection groove (trench) to a width thereof (an interconnection groove depth/width ratio), and a ratio of a depth of the interlayer connection hole for connecting the respective interconnections with each other to a diameter thereof (a connection hole depth/diameter ratio).
Further, as a result of shrinkage and higher integration of interconnection circuits, resistance of interconnections themselves has come to pose a problem. This is because an increase in the resistance of the interconnections will lead to delay in signal transmission. Accordingly, an attempt is being made to form Cu-based interconnections by use of an interconnection material based on Cu (hereinafter referred to also as a Cu-based interconnection material) capable of achieving reduction in electrical resistance more than a conventional interconnection material based on Al (hereinafter referred to also as an Al-based interconnection material)
As a method for forming the Cu-based interconnections of the multilayer structure, there has been known the damascene wiring technology (refer to, for example, Patent document 1). This technology is represented by a method whereby the interconnection grooves and the interlayer connection holes (hereinafter all those together are referred to also as recesses) are formed in an interlayer dielectric provided on a semiconductor substrate, surfaces of the interconnection grooves, and so forth are covered by the Cu-based interconnection material, such as pure Cu, Cu alloy, and so forth, and the Cu-based interconnection material is rendered fluid by applying heat thereto under pressure to be embedded in the recesses, thereby forming the interconnections.
In this connection, if the interlayer dielectric is in direct contact with the Cu-based interconnection material in the case of using the Cu-based interconnection material as the interconnection material, this will cause Cu to be diffused into the interlayer dielectric, thereby resulting in deterioration of insulation properties of the interlayer dielectric. Accordingly, in order to prevent diffusion of Cu into the interlayer dielectric, it is necessary to provide a barrier layer between the interlayer dielectric and the Cu-based interconnections. Because the barrier layer is required to exhibit blocking properties even when heated to a high temperature in a range of about 500 to 700° C. for causing the Cu-based interconnections to be embedded in the recesses, a metal nitride film, such as a TaN film, TiN film, and so forth, is used for the barrier layer. The barrier layer described, however, is high in electric resistivity in comparison with a metal film, thereby posing a problem of raising, in effect, an electric resistivity of the interconnections. It is difficult, however, to form the barrier layer so as to be small and uniform in thickness to thereby lower the electric resistivity of the interconnections. Moreover, as described in the foregoing, there has lately been a further decrease in the width of the interconnection groove, and the diameter of the connection hole while there has been a further increase in the interconnection groove depth/width ratio, and the connection hole depth/diameter ratio, so that it has become more difficult to form the barrier layer.
Under such circumstances as described, in order to uniformly form an extremely thin barrier layer on an interface between the Cu-based interconnections, and the interlayer dielectric, the inventor, et al. have already proposed formation of a Ti-concentration layer as the extremely thin barrier layer at the interface between the Cu-based interconnections, and the interlayer dielectric by taking advantage of a non-equilibrium solid solution phenomenon with much attention being focused on vapor quenching in the sputtering method (refer to Non-patent Document 1, and so forth). With this technology, a Cu-alloy containing Ti having a small solubility limit in relation to Cu is formed over the interconnection grooves, and the connection holes to be subsequently heated under pressure, thereby causing Cu and Ti to be separated into two phases, so that Ti is caused to undergo abnormal diffusion on the interface between the Cu-based interconnections, and the interlayer dielectric, or on the surface of the Cu-based interconnections, thereby forming the Ti-concentration layer. In particular, the Ti-concentration layer formed on the interface between the Cu-based interconnections, and the interlayer dielectric acts as the barrier layer for preventing the diffusion of Cu into the interlayer dielectric. Now, if the interlayer dielectric is an oxide based film (for example, an SiO2-base film), Ti diffused in the interface forms TiOx, however, if the Ti-concentration layer increase in thickness to some extent, reaction between Ti and oxygen comes to a stop, so that a thickness of the Ti-concentration layer does not become excessively large, and a rise in the electric resistivity of the interconnections can be controlled.
However, since the Cu-alloy containing Ti, even if heated to a high temperature, is poor in fluidity (hereinafter referred to also as reflow properties), it is difficult to embed the Cu-alloy into every corner of the recesses. Furthermore, as previously described, the width of the interconnection groove, and the diameter of the connection hole have lately become increasingly smaller while the interconnection groove depth/width ratio, and the connection hole depth/diameter ratio have lately become increasingly greater, so that it has become more difficult to embed the Cu-alloy into the recesses. [Patent Document 1] JP-A No. 7050/2001 (refer to Claims) [Non-patent Document 1] “Self-formation of Barrier Layer by Using Cu alloy interconnection”, draft papers for the 10th research conference, Research Society of Atom Migration and Stress Problem in LSI Interconnection(s) (2004, pp. 28 to 29)